The present invention generally relates to the field of computing, data processing and digital communications. More particularly, the described invention discloses a circuit and method for achieving hold time compatibility between datasource devices coupled to a data-requesting device, e.g., a processor, through a data bus.
Rapidly increasing information traffic as well as increased computational needs continue to push bus and processor limits as users demand faster computers and higher data transfer rates. As processing times increase, clock frequencies increase and clock periods decrease. These shorter clock cycles may result in problems when logic circuit processing speeds approach that of a clock cycle.
The correct operation of a logic circuit depends on certain timing criteria being satisfied. FIG. 1 depicts some exemplary timing criteria which generally needs to be satisfied. One criterion is that a sufficient setup time 104 is available, and a subsequent sufficient hold time 108 is available. The setup time 104 is the amount of time preceding the change of state 112 in a control signal 116, typically a clock transition, in which a data signal 120 must be kept steady in order for a logic circuit to properly process the data. The hold time 108 is the amount of time following the change in a control signal 112, again typically a clock transition 112, in which the data signal 120 must be held steady for a logic circuit to properly process the signal.
As further described below, the present invention addresses the need to have interface architectures that reliably and inexpensively provide compatible hold time between devices that may be coupled to a data-requesting device, e.g., a digital signal processor (DSP), through a data bus. For example, in microprocessor-based systems and, particularly, in systems using relatively fast integrated circuit (IC) digital signal processors (DSPs), the timing criteria should be satisfied by any hardware interfaces between the microprocessor or DSP and other devices connected to the bus, such as devices that source data to the DSP. As an example of the foregoing, a typical relatively fast, and presently commercially available DSP, such as Texas Instruments DSP model TMS320LC206-80 and others, may demand a hold time of approximately two ns when reading data signals from devices that are coupled to the data bus to source such data signals. Typical data-source devices, such as flash memories, etc., are specified by their respective manufacturers to have approximately zero ns hold time. In order to overcome the resulting conflict in the hold time, it is known to use IC bi-directional buffers to isolate the devices from the DSP so as to provide the requisite hold time. Unfortunately, use of such IC buffers adds to the complexity and cost of the interfacing architecture. For example, in a 32-bit parallel processor, each data line requires one respective IC buffer and consequently the interfacing hardware requires a total of at least 32 of such IC buffers. Thus, it is desired to provide a lowercost hardware solution to any data hold time conflicts that may arise in a processing system by eliminating use of higher cost IC components for lower cost passive or discrete components.
Generally speaking the present invention fulfills the foregoing needs by providing a circuit for achieving hold time compatibility between data-source devices coupled to a data-requesting device, e.g., a processor through a data bus. The circuit comprises an impedance coupled to the data bus, and the value of that impedance is selected, based on a respective capacitance in the data bus, to introduce a predetermined delay to data passing therethrough.
The present invention further fulfills the foregoing needs by providing a method for achieving hold time compatibility between data-source devices coupled to a data-requesting device, e.g., a processor through a data bus. The method allows for coupling an impedance to the data bus, and for selecting the value of that impedance, based on a respective capacitance in the data bus, to introduce a predetermined delay to data passing therethrough.